The present invention is directed generally to digital computing systems, and more particularly to a special-purpose, microprogrammed digital subsystem that operates as an adjunct of a central processor unit (CPU) of a computing system to relieve the CPU of many of the functions it would otherwise have to perform. The invention functions in response to sequences of instructions to provide a variety of control signals, and to test for the existence or non-existence of a variety if digital conditions.
Computing systems of the type to which the present invention is directed often include a variety of peripheral units with which the system's CPU must communicate for transfers of data. Typically, when the CPU requests a data transfer from a peripheral unit such as a disk drive unit, it will initiate a data transfer request. A period of time ensues before the request is horored, during which the peripheral device readies itself for the data transfer and, when ready, notifies the CPU that the transfer can, or is about to, take place. Because of the disparity in operating speeds between a typical CPU and the usual peripheral device (i.e., keyboards, disk and tape drives, (and the like) it is an inefficient use of CPU time to have the CPU connected to the peripheral device for an entire period of a data transfer.
The promblem is compounded when a number of peripheral devices are requested to transfer data and two or more of the peripheral devices respond to the requests at approximately the same time. In that case, the CPU must take time to determine which peripheral device will be first, which will be later, and then stay on-line to handle all requests, keeping the CPU from its normal computing chores.
In order to increase efficiency of the computing system the CPU is often provided with specially designed state machines or similar apparatus to handle certain of these adjunct operations, allowing the CPU to continue to execute the main program. Thus, for example, where the CPU will issue an input/output data transfer request, it can turn over responsibility for set-up of that transfer to a special-purpose subsystem that notifies the CPU only when the CPU is needed for effecting the data transfer. The special-purpose subsystem is provided with only that intelligence necessary to test for the occurrence or non-occurrence of conditions precedent to data transfers. The primary advantage of this type of configuration is speed since, in effect, multiple events are performed in parallel.
Often, the subsystem must test for the presence of conditions, and branch in the instruction sequence depending upon the presence or absence of the condition. The brance can penalize operation in the number of cycles necessary to ultimately reach the target instruction. Present technology has sought to reduce branch penalties by including branch prediction capability, at the cost of sometimes substantial additional circuit components. Other approaches include fetching two instructions and, at the same time, choosing which to execute on the basis of a test condition. Again, this latter technique increases speed at the cost of component count.